1. Field on the Invention
The present invention relates to a semiconductor memory device, and in particular, to a semiconductor memory device including a SRAM (static random access memory).
2. Description of the Prior Art
Semiconductor memory devices include volatile memories which can retain information only when power is being turned on, and nonvolatile memories which can retain information even when power is turned off. The volatile memories include a SRAM (static random access memory) and a DRAM (dynamic RAM), and the nonvolatile memories include a mask ROM (mask read only memory), a PROM (programmable ROM), an EPROM (erasable programmable ROM), and an EEPROM (electrically erasable and programmable ROM), and the like.
Among the volatile memories, the SRAM is frequently used in super computers and central portions of many computers, and in office automation equipment, and the like, because the timing of memory operation of the SRAM is easily achieved, no complicated refresh control is required thereby to facilitate the usage, and also the high speed operation is easily attained.
This SRAM has a structure, for example, as shown in FIG. 11, including switching transistors Q.sub.1 and Q.sub.4, driving transistors Q.sub.2 and Q.sub.3, and resistors R.sub.1 and R.sub.2. An inverter is formed by the driving transistor Q.sub.2 and the resistor R.sub.1, and another inverter is formed by the driving transistor Q.sub.3 and the resistor R.sub.2, and in these two inverters, the output of one inverter is an input of the other inverter, and vice versa. A storage node N.sub.1 at the junction point between the driving transistor Q.sub.2 and the resistor R.sub.1, and a storage node N.sub.2 at the junction point between the driving transistor Q.sub.3 and the resistor R.sub.2 are respectively connected to bit lines 200 through respective switching transistors Q.sub.1 and Q.sub.4. The gates of the switching transistors Q.sub.1 and Q.sub.4 are connected to a word line 100. Furthermore, the switching transistors Q.sub.1 and the driving transistor Q.sub.2 form another inverter (hereinafter referred to as a Q.sub.1 -Q.sub.2 inverter), and the driving transistor Q.sub.3 and the switching transistors Q.sub.4 form still another inverter (hereinafter referred to as a Q.sub.3 -Q.sub.4 inverter).
In this SRAM, a high potential of the storage nodes N.sub.1 and N.sub.2 corresponds to a logic "1", and a low potential of the storage nodes N.sub.1 and N.sub.2 corresponds to a logic "0". Specifically, when the storage nodes N.sub.1 is applied with a high potential, the driving transistor Q.sub.3 is turned on to make the storage node N.sub.2 to assume a low potential, and the driving transistor Q.sub.2 is turned off to hold the storage modes N.sub.1 at the high potential. Conversely, when the storage modes N.sub.1 is applied with a low potential, the storage node N.sub.2 is maintained at a high potential in a similar manner. This state is maintained as far as the power supply voltage is supplied, and as far as the potentials of the storage nodes N.sub.1 and N.sub.2 are not changed externally.
In the SRAM shown in FIG. 11, supposing that a certain memory cell (i-th row and j-th column) is designated. Here, when the word line 100 and a column selection line 300 are applied with a high voltage, since the switching transistors Q.sub.1, Q.sub.4, Q.sub.5, and Q.sub.6 are turned on, potentials of the storage nodes N.sub.1 and N.sub.2 are read out, or data is written into the storage nodes N.sub.1 and N.sub.2 through a common bit line 400. In FIG. 11, although the resistors R.sub.1 and R.sub.2 are intended to represent load members, these resistors may be replaced by load transistors.
In the above-mentioned SRAM, it is important to design the memory cell so that it operates stably against non-uniformity of pattern shapes of elements and noise margin.
FIG. 12 shows an input/output characteristic of the Q.sub.1 -Q.sub.2 inverter and an input/output characteristic of the Q.sub.3 -Q.sub.4 inverter with respect to potentials of the storage nodes N.sub.1 and N.sub.2 just after rewriting of the memory cell (at the time when the switching transistors are in a turned-on state). As shown in FIG. 12, an output potential of the Q.sub.3 -Q.sub.4 inverter with respect to an input signal potential V.sub.1 which is larger than a potential V.sub.T is represented by V.sub.2, and when this potential V.sub.2 is inputted to the Q.sub.1 -Q.sub.2 inverter, its output potential is represented by V.sub.3. From this, it will be seen that the output potential of the Q.sub.1 -Q.sub.2 inverter approaches a point A. Conversely, when a potential smaller than the potential V.sub.T is inputted to the Q.sub.3 -Q.sub.4 inverter, the output potential of the Q.sub.1 -Q.sub.2 inverter will approach a point D. As shown here, the potential V.sub.T is a boundary of logics "0" and "1" for the output of the storage node N.sub.1, and represents a threshold value voltage. In this respect, points A to D represent the following states.
Point A: writing when the storage node N.sub.1 is logic "1".
Point B: reading out when the storage node N.sub.1 is logic "1".
Point C: reading out when the storage node N.sub.1 is logic "0".
Point D: writing when the storage node N.sub.1 is logic "0".
It has been known that the memory cell can be operated more stably when the area of a hatched portion formed by the input/output characteristic curve of the Q.sub.1 -Q.sub.2 inverter and the input/output characteristic curve of the Q.sub.3 -Q.sub.4 inverter becomes larger. In order to increase the area of the hatched portion, it is necessary to increase a .beta. ratio of the switching transistors Q.sub.1 and Q.sub.4 to the driving transistors Q.sub.2 and Q.sub.3 as far as possible. In this respect, .beta. and the .beta. ratio is obtained from the following equations. ##EQU1##
Where, .mu..sub.N is the carrier mobility, C.sub.ox is the gate capacitance, W.sub.eff is the effective channel width, L.sub.eff is the effective channel length, .beta..sub.S is of the switching transistor, and .beta..sub.D is .beta. of the driving transistor.
Normally, it is known that a value of the .beta. ratio is suitably about 2.5 to 5. From the equation (1), it is seen that in order to increase the .beta. ratio as far as possible, .beta..sub.D may be increased as far as possible as compared with .beta..sub.S. In order to increase .beta..sub.D, it is required to increase the effective channel width of the driving transistor. As a result, the size of the driving transistor is made necessarily large. Accordingly, it becomes impossible to manufacture the driving transistor with a minimum size, and thus there is a problem in that the high integration of a semiconductor memory device is disturbed.
Furthermore, Japanese Patent Laid-Open Publication No. 62-230058 discloses a non-volatile semiconductor memory device including a SRAM and an EEPROM connected to each other. In this semiconductor memory device, the miniaturization and the high integration of the driving transistor are achieved by reducing a film thickness of a gate insulation film of the SRAM to the same thickness as the tunnel insulation film of EEPROM and reducing a resistance value thereby to reduce the area of the driving transistor. However, this prior art example relates to a semiconductor memory device having both the SRAM and the EEPROM, and it is not related to the SRAMs and logic LSI including SRAMs.